In a display device such as an active matrix liquid crystal display device, a plurality of data signal lines (also referred to as “source lines”), a plurality of scanning signal lines (also referred to as “gate lines”) that intersect with the plurality of data signal lines, and a plurality of pixel formation portions arranged in a matrix form along the plurality of data signal lines and the plurality of scanning signal lines are formed in a display unit of a liquid crystal panel or the like. Some of such active matrix display devices have employed a dot sequential driving system or an SSD (Source Shared Driving) system. The SSD system is a system in which the plurality of data signal lines in the display unit are divided into a plurality of data signal line groups, with a predetermined number of (two or more) data signal lines set as one group, and an analog video signal is provided to the predetermined number of data signal lines in each group in a time-division manner.
In the active matrix display device, when the dot sequential driving system or the SSD system is employed, an analog video signal is provided to each data signal line via an analog switch in an on-state, and then a level of a control signal for the analog switch is changed to bring the analog switch into an off-state, thereby holding a voltage of the analog video signal on the data signal line. Any of the above plurality of scanning signal lines is activated (selected) while the voltage of the analog video signal is held on each data signal line as thus described, whereby the voltage of the data signal line is written as pixel data into the pixel formation portion connected to the activated scanning signal line.
FIG. 9 is a circuit diagram showing a configuration of a portion (hereinafter referred to as “unit sample-and-hold circuit”) corresponding to one data signal line SLk in a sample-and-hold circuit for sampling an analog video signal and holding the sampled signal on each data signal line SLi (i=1 to N) in the display device as described above. This unit sample-and-hold circuit includes an N-channel field effect transistor (hereinafter abbreviated as “Nch transistor”) SWk as an analog switch, and a parasitic capacitance Cgd formed between a gate terminal of this Nch transistor SWk and one conductive terminal thereof which is connected to the data signal line SLk. An analog video signal Sv1 is provided to the other conductive terminal of the Nch transistor SWk, and a control signal Sck for controlling the on-off of the Nch transistor SWk is provided to the gate terminal of the Nch transistor SWk. The Nch transistor SWk (including the parasitic capacitance Cgd) as above constitutes a sampling circuit of the analog video signal Sv1, and this sampling circuit and a capacitance Csl of the data signal line SLk (a total capacitance formed by the data signal line SLk and the other electrodes) constitute the unit sample-and-hold circuit.
In the above sampling circuit, at the time of turning on the analog switch, an on-voltage (a high-level voltage (hereinafter referred to as “H-level voltage”) when the analog switch is made up of the Nch transistor) is provided as the control signal Sck to the gate terminal of the Nch transistor SWk, and at the time of turning off the analog switch, an off-voltage (a low-level voltage (hereinafter referred to as “L-level voltage”) when the analog switch is made up of the Nch transistor) is provided as the control signal Sck to the gate terminal of the Nch transistor SWk.
As shown in FIG. 10, when the H-level voltage VCH is provided as the control signal Sck to the gate terminal of the Nch transistor SWk, this Nch transistor SWk enters the on-state, and the analog video signal Sv1 is provided to the data signal line SLk via this Nch transistor SWk. As a result, a voltage Vsl of the data signal line SLk (hereinafter referred to as “data signal line voltage”) becomes equal to a voltage Vv1 of the analog video signal Sv1. Thereafter, when the voltage provided to the gate terminal of the Nch transistor SWk as the control signal Sck changes from an H-level voltage VCH to an L-level voltage VCL, the Nch transistor SWk enters the off-state. At this time, the voltage change (VCH to VCL) in the gate terminal of the Nch transistor SWk has an influence on the data signal line voltage Vsl via the parasitic capacitance Cgd, and the data signal line voltage Vsl decreases from the voltage Vv1 of the analog video signal Sv1 in accordance with the voltage change. This voltage decrease amount ΔVsl is expressed by the following formula, assuming that the above voltage change instantly occurs (assuming that the Nch transistor SWk instantly shifts to the off-state):ΔVsl={Cgd/(Csl+Cgd)}(VCH−VCL)  (1)
Further, in the active matrix liquid crystal display device, also in each pixel formation portion, a voltage Vp of a pixel electrode (hereinafter referred to as “pixel voltage”) decreases due to a parasitic capacitance in a transistor (normally a thin-film transistor) as a pixel switching element at the time of turning off the switching element (hereinafter assumed to be made up of the Nch transistor) (see FIGS. 14 and 15). At this time, the pixel voltage decrease amount ΔVp is expressed by the following formula, where a pixel capacitance is represented by “Cp”, assuming that a voltage of a scanning signal that is provided to the gate terminal of the Nch transistor instantly changes from an H-level gate voltage VGH as the on-voltage to an L-level gate voltage VGL as the off-voltage, namely, the Nch transistor as the pixel switching element instantly shifts to the off-state:ΔVp={Cgd/(Cp+Cgd)}(VGH−VGL)  (2)
As an invention related to the present application, Patent Document 1 describes an invention of an active matrix display device of the SSD system. For the purpose of reducing power consumption in driving a switch unit for data-line selection, this display device is provided with a switch unit drive circuit configured so as to switch a voltage level between an on-voltage and an off-voltage of a data line selection signal through a period for an intermediate voltage. Further, Patent Document 2 describes an invention of a liquid crystal display panel scanning line driver configured such that a scanning line driving voltage (output signal) does not fall abruptly, but shows a gentle falling waveform in accordance with a drive capability of a switching element. This invention is aimed to prevent flickering of the screen by taking a measure capable of reducing a variation ΔV in a display electrode voltage that occurs when the output signal of the scanning line driver shifts from “H” to “L”.